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AC'97 2.1 FEATURES Variable Sample Rate Audio Multiple Codec Configuration Options External Audio Power-Down Control
AC'97 SoundMAX(R) Codec AD1885
ENHANCED FEATURES Full Duplex Variable Sample Rates from 7040 Hz to 48 kHz with 1 Hz Resolution Jack Sense Pins Provide Automatic Output Switching Software-Enabled VREFOUT Output for Microphones and External Power Amp Split Power Supplies (3.3 V Digital/5 V Analog) Mobile Low-Power Mixer Mode Extended 6-Bit Master Volume Control Extended 6-Bit Headphone Volume Control Digital Audio Mixer Mode PHATTM Stereo 3D Stereo Enhancement
AC'97 FEATURES AC'97 2.1-Compliant Greater than 90 dB Dynamic Range Stereo Headphone Amplifier Multibit Converter Architecture for Improved S/N Ratio Greater than 90 dB 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for: LINE-IN, CD, VIDEO, and AUX Two Analog Line-Level Mono Inputs for Speakerphone and PC BEEP Mono MIC Input w/Built-In 20 dB Preamp, Switchable from Two External Sources High Quality CD Input with Ground Sense Stereo Line-Level Outputs Mono Output for Speakerphone or Internal Speaker Power Management Support 48-Terminal LQFP Package FUNCTIONAL BLOCK DIAGRAM
ID0 ID1 JS0/EAPD JS1
AD1885
CHIP SELECT MIC1 MIC2 LINE
SELECTOR
JACK SENSES AND EAPD CTRL
VREF
VREFOUT
0dB/ 20dB
AUX CD VIDEO PHONE_IN
PGA
16-BIT A/D CONVERTER
PGA
16-BIT A/D CONVERTER
RESET
SYNC MONO_OUT MMV G A M POP PHAT STEREO NC G A M 16-BIT D/A CONVERTER G A M G A M G A M G A M G A M
AC LINK
SAMPLE RATE GENERATORS
BIT_CLK
HP_OUT_L
HV
SDATA_OUT
LINE_OUT_L
MV
SDATA_IN
LINE_OUT_R
MV
POP
PHAT STEREO G = GAIN A = ATTENUATE M = MUTE MV = MASTER VOLUME HV = HEADPHONE VOLUME
NC A M
G A M
16-BIT D/A CONVERTER
HP_OUT_R
HV
OSCILLATOR
PC_BEEP
XTL_OUT XTL_IN
SoundPort is a registered trademark and PHAT is a trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD1885-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (FS) Input Signal Analog Output Passband 25 C 3.3 V 5.0 V 48 kHz 1008 Hz 20 Hz to 20 kHz DAC Test Conditions Calibrated -3 dB Attenuation Relative to Full Scale Input 0 dB 10 k Output Load (LINE_OUT) 32 Output Load (HP_OUT) ADC Test Conditions Calibrated 0 dB Gain Input -3.0 dB Relative to Full Scale ANALOG INPUT Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP MIC with 20 dB Gain (M20 = 1) MIC with 0 dB Gain (M20 = 0) Input Impedance* Input Capacitance*
MASTER VOLUME
Min
Typ 1 2.83 0.1 0.283 1 2.83 20 5
Max
Unit V rms V p-p V rms V p-p V rms V p-p k pF
7.5
Parameter Step Size (0 dB to -94.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range Span* Step Size (0 dB to -46.5 dB); MONO_OUT Output Attenuation Range Span* Step Size (+6 dB to -88.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range Span* Mute Attenuation of 0 dB Fundamental*
PROGRAMMABLE GAIN AMPLIFIER--ADC
Min
Typ 1.5 -94.5 1.5 -46.5 1.5 -94.5
Max
Unit dB dB dB dB dB dB dB
80
Parameter Step Size (0 dB to 22.5 dB) PGA Gain Range Span
ANALOG MIXER--INPUT GAIN/AMPLIFIERS/ATTENUATORS
Min
Typ 1.5 22.5
Max
Unit dB dB
Parameter Signal-to-Noise Ratio (SNR) CD to LINE_OUT Other to LINE_OUT Step Size (+12 dB to -34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC Input Gain/Attenuation Range: MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC Step Size (0 dB to -45 dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP
* Guaranteed, not tested.
Min
Typ 90 90 1.5 -46.5 3.0 -45
Max
Unit dB dB dB dB dB dB
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AD1885
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband
ANALOG-TO-DIGITAL CONVERTERS
Min 0 0.4 x FS 0.6 x FS -74
Typ
Max 0.4 x FS 0.09 0.6 x FS 12/FS 0.0
Unit Hz dB Hz Hz dB sec s
Parameter Resolution Total Harmonic Distortion (THD Dynamic Range (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) LINE_IN to Other Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Min
Typ 16 -84 87 85 -100 -90
Max
Unit Bits dB dB dB
84
-90 -85 10 0.5 5
dB dB % dB mV
Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT (With 10 k Load) Dynamic Range LINE_OUT (-60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative to Nominal Input Voltage) Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT) Total Audible Out-of-Band Energy (Measured from 0.6 x FS to 20 kHz)*
ANALOG OUTPUT
Min
Typ 16 -85 -75
Max
Unit Bits dB dB dB dB % dB dB dB
85
90 -100 10
0.7 -80
-40
Parameter Full-Scale Output Voltage; LINE_OUT Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance Full-Scale Output Voltage; HP_OUT (0 dB Gain) Output Capacitance* External Load Capacitance VREF VREFOUT VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
*Guaranteed, not tested.
Min
Typ 1 2.83
Max
Unit V rms V p-p k pF pF V rms pF V V mA mV
800 10 15 100 1 100 32 2.45 5 5
2.05
2.25 2.25
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AD1885-SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS*
Parameter High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), IOH = 2 mA Low-Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current
POWER SUPPLY
Min 0.65 x DVDD 0.9 x DVDD -10 -10
Typ
Max
Unit
V 0.35 x DVDD V V 0.1 x DVDD V 10 A 10 A
Parameter Power Supply Range--Analog (AVDD) Power Supply Range--Digital (DVDD) Power Dissipation--5 V/3.3 V Analog Supply Current--5 V (AVDD) Digital Supply Current--3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal @ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs)
CLOCK SPECIFICATIONS
Min 4.75 3.15
Typ
Max 5.25 3.45
Unit V V mW mA mA dB
355 50 21 40
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN MODE*
Min 40
Typ 24.576 50
Max 60
Unit MHz %
Parameter ADC DAC ADC and DAC ADC + DAC + Mixer (Analog CD On) Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Analog CD Only (AC-Link On) Analog CD Only (AC-Link Off) Standby Headphone Standby
Set Bits PR0 PR1 PR1, PR0 LPMIX, PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 LPMIX, PR5, PR1, PR0 LPMIX, PR1, PR0, PR4, PR5 PR5, PR4, PR3, PR2, PR1, PR0 PR6
DVDD (3.3 V) Typ 20 20 8 8 21 19 19 8 7 0 0 21
AVDD (5 V) Typ 44 41 35 26 23 18 15 10 22 12 0.1 38
Unit mA mA mA mA mA mA mA mA mA mA mA mA
NOTES *Guaranteed, not tested. Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice.
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TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Low Pulsewidth RESET Inactive to BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Low Pulsewidth SYNC Inactive to BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Low Pulsewidth SYNC Frequency SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time End of Slot 2 to BIT_CLK, SDATA_IN Low Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) Rising Edge of RESET to HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
NOTES *Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
Min 162.8
Typ 1.0 1.3 19.5
Max
Unit s ns s s ns MHz ns ps ns ns kHz s ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns
162.8 12.288 81.4 32.56 32.56 42 38 48.0 20.8 2.5 4 4 4 4 4 4 4 4 750 48.84 48.84
5 5 2 2 2 2 2 2 2 2 0 15
10 10 10 10 10 10 10 10 10 25 15 50 15
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AD1885
tRST_LOW
RESET
tRST2CLK
BIT_CLK
tRISECLK
SYNC
tFALLCLK
BIT_CLK
Figure 1. Cold Reset
tRISESYNC
SDATA_IN
tFALLSYNC
tSYNC_HIGH
SYNC BIT_CLK
tRST2CLK
SDATA_OUT
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
Figure 2. Warm Reset
Figure 5. Signal Rise and Fall Time
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD
SYNC
SLOT 1
SLOT 2
BIT_CLK
tSYNC_LOW
SYNC
SDATA_OUT
WRITE TO 0x26
DATA PR4
DON'T CARE
tSYNC_HIGH tSYNC_PERIOD
SDATA_IN
tS2_PDOWN
NOTE: BIT_CLK NOT TO SCALE
Figure 3. Clock Timing
Figure 6. AC-Link Low Power Mode Timing
tSETUP
RESET
BIT_CLK
SDATA_OUT
SYNC SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK HI-Z
tHOLD
tOFF
Figure 4. Data Setup and Hold
Figure 7. ATE Test Mode
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AD1885
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter Power Supplies Digital (AVDD) Analog (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
Min -0.3 -0.3 -0.3 -0.3 0 -65
Max +3.6 +6.0 10 AVDD + 0.3 DVDD + 0.3 70 +150
Unit Model V V mA V V C C AD1885JST
Temperature Range 0C to 70C
Package Description 48-Lead LQFP
Package Option* ST-48
*ST = Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in t he operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Ambient Temperature Rating TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) Package LQFP
JA JC CA
76.2C/W
17C/W
59.2C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1885 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
MONO_OUT
36 LINE_OUT_R 35 LINE_OUT_L 34 CX3D 33 RX3D 32 FILT_L 31 FILT_R 30 AFILT2 29 AFILT1 28 VREFOUT 27 VREF 26 AVSS1 25 AVDD1 13 14 15 16 17 18 19 20 21 22 23 24
JS0 (EAPD)
NC HP_OUT_R AVSS2 CD_GND_REF CD_R MIC1
48 47 46 45 44 43 42 41 40 39 38 37
DVDD1 1 XTL_IN 2 XTL_OUT 3 DVSS1 4 SDATA_OUT 5 BIT_CLK 6 DVSS2 7 SDATA_IN 8 DVDD2 9 SYNC 10 RESET 11 PC_BEEP 12
PIN 1 IDENTIFIER
AD1885
TOP VIEW (Not to Scale)
VIDEO_R CD_L
PHONE_IN AUX_L
AUX_R VIDEO_L
MIC2
NC = NO CONNECT
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LINE_IN_L LINE_IN_R
HP_OUT_L AVDD2
ID0 AVSS3 AVDD3
JS1
ID1
AD1885-SPECIFICATIONS
PIN FUNCTION DESCRIPTIONS Digital I/O
Pin Name XTL_IN XTL_OUT SDATA_OUT BIT_ CLK SDATA_IN SYNC RESET
CHIP SELECTS
LQFP 2 3 5 6 8 10 11
I/O I O I O/I O I I
Description Crystal (or Clock) Input, 24.576 MHz. Crystal Output. AC-Link Serial Data Output, AD1885 Input Stream. AC-Link Bit Clock. 12.288 MHz Serial Data Clock. Daisy Chain Input Clock. AC-Link Serial Data Input. AD1885 Output Stream. AC-Link Frame Sync. AC-Link Reset. AD1885 Master H/W Reset.
Pin Name ID0 ID1
LQFP 45 46
Type I I
Description Chip Select Input 0 (Active Low). Chip Select Input 1 (Active Low).
JACK SENSES/EAPD/GENERAL-PURPOSE DIGITAL OUTPUTS
These signals can sense the presence of audio jacks in the line-out or headphones outputs, and automatically mute the other audio outputs. JS0 can also be programmed for EAPD control. Alternatively, both pins can be programmed as general-purpose digital outputs. Pin Name JS0 JS1
Analog I/O
LQFP 47 48
Type I/O I/O
Description JACK Sense Input 0 (Mutes Mono Output). JACK Sense Input 1 (Mutes Line_Out and Mono Outputs, or Line_Out Only).
These signals connect the AD1885 component to analog sources and sinks, including microphones and speakers. Pin Name PC_BEEP PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_ R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R LQFP 12 13 14 15 16 17 18 19 20 21 22 23 24 35 36 37 39 41 I/O I I I I I I I I I I I I I O O O O O Description PC Beep. PC speaker beep passthrough. Phone Input. From telephony subsystem speakerphone or handset. Auxiliary Input Left Channel. Auxiliary Input Right Channel. Video Audio Left Channel. Video Audio Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference for Differential CD Input. CD Audio Right Channel. Microphone 1. Desktop microphone input. Microphone 2. Second microphone input. Line In Left Channel. Line In Right Channel. Line Out Left Channel. Line Out Right Channel. Monaural Output to Telephony Subsystem Speakerphone. Headphones Out Left Channel. Headphones Out Right Channel.
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Filter/Reference
These signals are connected to resistors, capacitors, or specific voltages. Pin Name VREF VREFOUT AFILT1 AFLIT2 FILT_R FILT_L RX3D CX3D LQFP 27 28 29 30 31 32 33 34 I/O O O O O O O O I Description Voltage Reference Filter. Voltage Reference Output 5 mA Drive (Intended for Mic Bias). Antialiasing Filter Capacitor--ADC Right Channel. Antialiasing Filter Capacitor--ADC Left Channel. AC-Coupling Filter Capacitor--ADC Right Channel. AC-Coupling Filter Capacitor--ADC Left Channel. 3D PHAT Stereo Enhancement--Resistor. 3D PHAT Stereo Enhancement--Capacitor.
Power and Ground Signals
Pin Name DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3
No Connects
LQFP 1 4 7 9 25 26 38 40 43 44
Type I I I I I I I I I I
Description Digital VDD 3.3 V Digital GND Digital GND Digital VDD 3.3 V Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND Analog VDD 5.0 V Analog GND
Pin Name NC
LQFP 42
Type
Description No Connect
ID0
ID1
JS0/EAPD
JS1
CHIP SELECT MIC1 0 MS MIC2 LINE AUX CD VIDEO PHONE_IN STEREO MIX (L) MONO MIX STEREO MIX (R) MV MIX 0x20 GA 0x0C PHV M 0x0C PHM POP 0x02 LINE_OUT_L MM 0x02 LINE_OUT_R MM LMV LMV 0x02 0x02 D A M 0x22 DP 0x22 DP PHAT 0x20 PHAT 0x20 POP 0x04 HP_OUT_R HPM RHV 0x04 M 0x0A PCM A 0x0A PCV PC_BEEP GA 0x0E MCV M 0x0E MCM 1 0dB/20dB M20 0x0E
JACK SENSE AND EAPD CTRL LS/RS (0) LS (4) RS (4) S E LS (3) L RS (3) E LS (1) C RS (1) T LS (2) O RS (2) R LS/RS (7) LS (5) LS/RS (6) RS (5) GA 0x10 LLV RLV M 0x10 LM GA 0x12 LCV RCV M 0x12 CM GA 0x16 LAV RAV M 0x16 AM GA 0x14 LVV RVV M 0x14 VM S 0x1A
VREF
VREFOUT
S 0 20
GAM 0x1C LIV IM
GAM 0x1C RIV IM RESET
MONO_OUT
AC-LINK
SYNC BIT_CLK SDATA_OUT SDATA_IN
AD1885
0x04 HP_OUT_L HPM
0x04 LHV
A NC 3D 0x20 SWITCH NC B
GAM 0x18 LOV OM
GAM 0x18 ROV OM
G = GAIN A = ATTENUATION M = MUTE S = SELECTOR
OSCILLATORS
XTL_OUT
XTL_IN
Figure 8. Block Diagram Register Map
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AD1885
PRODUCT OVERVIEW Sample Rates and D2S
The AD1885 Codec meets the Audio Codec '97 2.1 Extensions, adding support for multiple Codecs and variable sample rates. In addition, the AD1885 SoundPort Codec is designed to meet all requirements of the Audio Codec '97, Component Specification, Revision 1.03, (c) 1996, Intel Corporation, found at www.Intel.com. The AD1885 also includes other Codec enhanced features such as communicating to three Codecs on the same link, integrated headphone driver and built-in PHAT Stereo 3D enhancement. The AD1885 is an analog front end for high-performance PC audio, modem, or DSP applications. The AC'97 architecture defines a 2-chip audio solution comprising a digital audio controller, plus a high-quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs), mixer, and I/O. The main architectural features of the AD1885 are the high quality analog mixer section, two channels of ADC conversion, two channels of DAC conversion and Data Direct Scrambling (D2S) rate generators.
FUNCTIONAL DESCRIPTION
The AD1885 default mode sets the Codec to operate at 48 kHz sample rates. The converter pairs may process left and right channel data at different sample rates. The AD1885 sample rate generator allows the Codec to instantaneously change and process sample rates from 7040 Hz to 48 kHz with a resolution of 1 Hz. The in-band integrated noise and distortion artifacts introduced by rate conversions are below -90 dB. The AD1885 uses a 4-bit structure and D2S to enhance noise immunity on motherboards and in PC enclosures, and to suppress idle tones below the device's quantization noise floor. The D2S process pushes noise and distortion artifacts caused by errors in the multibit DAC to frequencies beyond the auditory response of the human ear and then filters them.
Digital-to-Analog Signal Path
The analog output of the DAC may be gained or attenuated from +12 dB to -34.5 dB in 1.5 dB steps, and summed with any of the analog input signals. The summed analog signal enters the Master Volume stage where each channel of the mixer output may be attenuated from 0 dB to -94.5 dB in 1.5 dB steps or muted.
Analog Outputs
This section overviews the functionality of the AD1885 and is intended as a general introduction to the capabilities of the device. Detailed reference information may be found in the descriptions of the Indexed Control Registers.
Analog Inputs
The AD1885 offers a line output controlled by the Master Volume control and an integrated headphone driver with independent control.
Host-Based Echo Cancellation Support
The Codec contains a stereo pair of ADCs. Inputs to the ADC may be selected from the following analog signals: telephony (PHONE_IN), mono microphone (MIC1 or MIC2), stereo line (LINE_IN), auxiliary line input (AUX), stereo CD ROM (CD), stereo audio from a video source (VIDEO) and post-mixed stereo or mono line output (LINE_OUT).
Analog Mixing
The AD1885 supports time correlated I/O data format by presenting mic data on the left channel of the ADC and the mono summation of left and right output on the right channel. The ADC is splittable; left and right ADC data can be sampled at different rates.
Telephony Modem Support
PHONE_IN, MIC1 or MIC2, LINE_IN, AUX, CD, and VIDEO can be mixed in the analog domain with the stereo output from the DACs. Each channel of the stereo analog inputs may be independently gained or attenuated from +12 dB to -34.5 dB in 1.5 dB steps. The summing path for the mono inputs (PHONE_IN, MIC1, and MIC2 to LINE_OUT and HP_OUT) duplicates mono channel data on both the left and right LINE_OUT and HP_OUT. Additionally, the PC attention signal (PC_BEEP) may be mixed with the line output and headphone. A switch allows the output of the DACs to bypass the PHAT Stereo 3D enhancement.
Digital Audio Mode
The AD1885 contains a V.34-capable analog front end for supporting host-based and data pump modems. The modem DAC typical dynamic range is 90 dB over a 4.2 kHz analog output passband where FS = 12.8 kHz. The left channel of the ADC and DAC may be used to convert modem data at the same sample rate in the range between 7040 Hz and 48 kHz. All programmed sample rates have a resolution of 1 Hz. The AD1885 supports irrational V.34 sample rates with 8/7 and 10/7 selectable multiplier coefficients.
Power Management Modes
The AD1885 is designed with a Digital Audio Mode (DAM) that allows mixing of all analog inputs, independent of the DAC output signal path. Mixed analog input signals may be sent to the ADCs for processing by the DC '97 controller or the host, and may be used during simultaneous capture and playback at different sample rates.
Analog-to-Digital Signal Path
The AD1885 is designed to meet notebook and ACPI power consumption requirements through flexible power management control of all internal resources. The following subsections may be independently controlled: ADCs and Input Mux Power-Down DACs Power-Down Analog Mixer Power-Down Digital Interface Power-Down Internal Clocks Disabled ADC and DAC Power-Down VREF Standby Mode Low-Power Mixer Mode--CD Mixer Alive Only Mode Mixer Bypass Mode (Digital Audio) Headphone
The selector sends left and right channel information to the programmable gain amplifier (PGA). The PGA following the selector allows independent gain control for each channel entering the ADC from 0 dB to +22.5 dB in 1.5 dB steps. Each channel of the ADC is independent, and can process left and right channel data at different sample rates.
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Indexed Control Registers
Reg Num 00h 02h 04h 06h Name Reset Master Volume Headphones Volume Master Volume Mono D15 X MM HPM MMM D14 SE4 X X X D13 SE3 LMV5 LHV5 X D12 SE2 D11 SE1 D10 SE0 D9 ID9 D8 ID8 D7 ID7 D6 ID6 X X X D5 ID5 RMV5 RHV5 X D4 ID4 RMV4 RHV4 MMV 4 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 26h 28h 2Ah 2Ch/ (7Ah)* 32h/ (78h)* 34h .. 72h Reserved .. Jack Sense/Audio Interrupt/Status 74h Serial Configuration X .. X .. X .. JS1 X .. JS0 X .. JS1_ X .. JS0 OE X X .. JS1 DIS X .. JS0 DIS X .. JS1 CLR X .. JS0_ CLR X X .. JS1 X .. JS0 X .. AUD X .. JS1 X .. JS0 X .. JS INT X X X 7000h X .. 0000h PCM ADC Rate (SR0) SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h Reserved PC Beep Volume Phone In Volume MIC Volume Line In Volume CD Volume Video Volume Aux Volume PCM Out Volume Record Select Record Gain Reserved General Purpose 3D Control Power-Down Cntrl/Stat Extended Audio ID X PCM PHM MCM LM CVM VM AM OM X IM X POP X X ID1 X X X X X X X X X X X X X X X ID0 X X X X X X X X X X X X X 3D X PR5 X X X X X X LLV4 X X X X X X X X X X X X LLV1 LCV1 LVV1 LAV1 LOV1 LS1 LIM1 X MIX X PR1 X X SR9 X X X X LLV0 LCV0 LVV0 LAV0 LOV0 LS0 LIM0 X MS X PR0 X X SR8 X X X X X X X X X X X X X X X M20 X X X X X X X X X X X X X X X X X X X X X X X X X SR5 X PCV3 PHV4 D3 ID3 D2 ID2 D1 ID1 D0 ID0 Default 0410h 8000h 8000h 8000h
LMV4 LMV3 LMV2 LMV1 LHV4 LHV3 LHV2 X X X LHV1 X
LMV0 X LHV0 X X X
RMV3 RMV2 RMV1 RMV0 RHV3 RHV2 MMV MMV 3 X PCV2 2 X PCV1 RHV1 RHV0 MMV MMV 1 X PCV0 0 X X
X 8000h 8008h
PHV3 PHV2
PHV1 PHV0
MCV4 MCV3 MCV2 MCV1 MCV0 8008h RLV4 RCV4 RVV4 RAV4 ROV4 X X X X X X X X SR4 RLV3 RLV2 RLV1 RLV0 8808h 8808h 8808h 8808h 8808h 0000h 8000h X 0000h 0000h 000Xh 0001h 0000h BB80h
LLV3 LLV2
LCV4 LCV3 LCV2 LVV4 LAV4 LVV3 LVV2 LAV3 LAV2
RCV3 RCV2 RVV3 RVV2
RCV1 RCV0 RVV1 RVV0
RAV3 RAV2 ROV3 ROV2 X RIM3 X X DP3 REF X X SR3 RS2 RIM2 X X DP2 ANL X X SR2
RAV1 RAV0 ROV1 ROV0 RS1 RIM1 X X DP1 DAC X X SR1 RS0 RIM0 X X DP0 ADC VRA VRA SR0
LOV4 LOV3 LOV2 X X X X X PR4 X X SR12 X LS2
LIM3 LIM2 X X X PR3 X X SR11 X X X PR2 X X SR10
LPBK X X X X X SR7 X X X X SR6
Extended Audio Stat/Ctrl X PCM DAC Rate (SR1) SR15
SR14 SR13
JS1_OUT JS0_ FUNCT SLOT 16
OUT PUDIS PUDIS OE REG M2 REG M1 REG M0 DAM DMS X
MODE MODE INT X X X
DHWR X
76h
Miscellaneous Control Bits
DAC Z F7 T7
LPMI X X F6 T6 F5 T5
DLSR
X
ALSR
MOD SRX1 SRX8 EN 0D7 S6 D7 S5
X
X
DRSR X
ARSR
0404h
7Ch 7Eh
Vendor ID1 Vendor ID2
F4 T4
F3 T3
F2 T2
F1 T1
F0 T0
S7
S4 REV4
S3 REV3
S2 REV2
S1 REV1
S0 REV0
4144h 5360h
REV7 REV6 REV5
NOTES All registers not shown and bits containing an X are assumed to be reserved. Odd register addresses are aliased to the next lower even address. Reserved registers should not be written. Zeros should be written to reserved bits. *Indicates Aliased register for AD1819B backward compatibility.
REV. 0
-11-
AD1885
Reset (Index 00h)
Reg Name Num 00h Reset D15 X D14 SE4 D13 SE3 D12 SE2 D11 SE1 D10 SE0 D9 D9 ID9 D8 D8 ID8 D7 D7 ID7 D6 D6 ID6 D5 D5 ID5 D4 D4 ID4 D3 D3 ID3 D2 D2 ID2 D1 D1 ID1 D0 D0 ID0 Default 0410h
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement. ID[9:0] Identify Capability. The ID decodes the capabilities of AD1885 based on the following: Bit = 1 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 Function Dedicated MIC PCM In Channel Modem Line Codec Support Bass and Treble Control Simulated Stereo (Mono to Stereo) Headphone Out Support Loudness (Bass Boost) Support 18-Bit DAC Resolution 20-Bit DAC Resolution 18-Bit ADC Resolution 20-Bit ADC Resolution AD1885 0 0 0 0 1 0 0 0 0 0
SE[4:0] Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Master Volume Registers (Index 02h)
Reg Num 02h Name Master Volume D15 MM MM D14 X D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 X
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
RMV[5:0] LMV[5:0] MM
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -94.5 dB. Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of -94.5 dB. Master Volume Mute. When this bit is set to "1," the channel is muted. MM 0 0 0 1 xMV5 . . . xMV0 00 0000 01 1111 11 1111 xx xxxx Function 0 dB Attenuation -46.5 dB Attenuation -94.5 dB Attenuation - dB Attenuation
-12-
REV. 0
AD1885
Headphones Volume Registers (Index 04h)
Reg Num 04h Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Headphones Volume HPM X
LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 X
X
RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h
RHV[5:0] LHV[5:0] HPM
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of -88.5 dB. Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output from +6 dB to a maximum attenuation of -88.5 dB. Headphone Volume Mute. When this bit is set to "1," the channel is muted. HPM 0 0 0 1 xHV5 . . . xHV0 00 0000 01 1111 11 1111 xx xxxx Function 6 dB Gain -40.5 dB Attenuation -88.5 dB Attenuation - dB Attenuation
Master Volume Mono (Index 06h)
Reg Num 06h Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Master Volume MMM X Mono
X
X
X
X
X
X
X
X
X
MMV4 MMV3 MMV2 MMV1 MMV0 8000h
MMV[4:0] MMM
Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from 0 dB to a maximum attenuation of 46.5 dB. Mono Master Volume Mute. When this bit is set to "1," the channel is muted.
PC Beep Register (Index 0Ah)
Reg Num 0Ah Name PC_BEEP Volume D15 PCM D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default 8000h
PCV3 PCV2 PCV1 PCV0 X
PCV[3:0]
PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output from 0 dB to a maximum attenuation of -45 dB. The PC Beep is routed to Left and Right Line outputs even when AD1885 is in a RESET state. This is so that Power-On Self-Test (POST) codes can be heard by the user in case of a hardware problem with the PC. PC Beep Mute. When this bit is set to "1," the channel is muted. PCM 0 0 1 PCV3 . . . PCV0 0000 1111 xxxx Function 0 dB Attenuation -45 dB Attenuation dB Attenuation
PCM
REV. 0
-13-
AD1885
Phone Volume (Index 0Ch)
Reg Num 0Ch Name Phone Volume D15 PHM D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
PHV[4:0] PHM
Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Phone Mute. When this bit is set to "1," the channel is muted.
MIC Volume (Index 0Eh)
Reg Name Num 0Eh MIC Volume D15 D14 D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 M20 D5 D5 X D4 D4 MCV4 D3 D3 MCV3 D2 D2 MCV2 D1 D1 MCV1 D0 D0 MCV0 Default 8008h
MCM X
MCV[4:0] M20
MIC Volume Gain. Allows setting the MIC Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Microphone 20 dB Gain Block 0 = Disabled; Gain = 0 dB 1 = Enabled; Gain = 20 dB. MIC Mute. When this bit is set to "1," the channel is muted.
MCM
Line In Volume (Index 10h)
Reg Name Num 10h D15 D14 D13 D12 X X D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 RLV4 D3 D3 RLV3 D2 D2 RLV2 D1 D1 RLV1 D0 D0 RLV0 Default 8808h
LM Line In Volume LM
LLV4 LLV3 LLV2 LLV1 LLV0
RLV[4:0] LLV[4:0] LM
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Line In Mute. When this bit is set to "1," the channel is muted.
CD Volume (Index 12h)
Reg Name Num 12h D15 D14 D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
CD Volume CVM X
LCV4 LCV3 LCV2 LCV1 LCV0
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0] LCV[4:0] CVM
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. CD Volume Mute. When this bit is set to "1," the channel is muted.
-14-
REV. 0
AD1885
Video Volume (Index 14h)
Reg Name Num 14h D15 D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Video Volume VM VM
LVV4 LVV3 LVV2 LVV1 LVV0
RVV4 RVV3 RVV2 RVV1 RVV0 8808h
RVV[4:0] LVV[4:0] VM
Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Video Mute. When this bit is set to "1," the channel is muted.
AUX Volume (Index 16h)
Reg Name Num 16h Aux Volume D15 AM AM D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LAV4 LAV3 LAV2 LAV1 LAV0
RAV4 RAV3 RAV2 RAV1 RAV0 8808h
RAV[4:0] LAV[4:0] AM
Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Aux Mute. When this bit is set to "1," the channel is muted.
PCM Out Volume (Index 18h)
Reg Name Num 18h PCM Out Volume D15 OM OM D14 X D13 X D12 D11 D10 D9 D9 D8 D8 D7 D7 X D6 D6 X D5 D5 X D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
LOV4 LOV3 LOV2 LOV1 LOV0
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0] LOV[4:0] OM
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the range is +12 dB to -34.5 dB. The default value is 0 dB, mute enabled. PCM Out Volume Mute. When this bit is set to "1," the channel is muted.
Volume Table
xM 0 0 0 1
x4 . . . x0 00000 01000 11111 xxxxx
Function +12 dB Gain 0 dB Gain -34.5 dB Gain - dB Gain
REV. 0
-15-
AD1885
Record Select Control Register (Index 1Ah)
Reg Name Num 1Ah D15 D14 X D13 X D12 X D11 X D10 LS2 D9 D9 LS1 D8 D8 LS0 D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 RS2 D1 D1 RS1 D0 D0 RS0 Default 0000h
Record Select X
RS[2:0] LS[2:0]
Right Record Select Left Record Select.
Used to select the record source independently for right and left. See table for legend. The default value is 0000h, which corresponds to MIC in. RS2 . . . RS0 0 1 2 3 4 5 6 7 LS2 . . . LS0 0 1 2 3 4 5 6 7
Record Gain (Index 1Ch)
Reg Name Num 1Ch Record Gain D15 IM IM D14 X D13 X D12 X D11 LIM3 D10 LIM2 D9 D9 LIM1 D8 D8 LIM0 D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 RIM3 D2 D2 RIM2 D1 D1 RIM1 D0 D0 RIM0 Default 8000h
Right Record Source MIC CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mix (R) Mono Mix PHONE_IN Left Record Source MIC CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mix (L) Mono Mix PHONE_IN
RIM[3:0] LIM[3:0] IM
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB. Input Mute. 0 = Unmuted, 1 = Muted or - dB gain. IM 0 0 1 xIM3 . . . xIM0 1111 0000 xxxxx Function +22.5 dB Gain 0 dB Gain - dB Gain
-16-
REV. 0
AD1885
General-Purpose Register (Index 20h)
Reg Name Num 20h General-Purpose D15 POP D14 X D13 3D 3D D12 X D11 X D10 X D9 D9 MIX D8 D8 MS MS D7 D7 LPBK D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 X Default 0000h
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. LPBK MS Loopback Control. ADC/DAC Digital Loopback Mode MIC Select 0 = MIC1 1 = MIC2. Mono Output Select 0 = Mix 1 = MIC. 3D PHAT Stereo Enhancement 0 = PHAT Stereo is off. 1 = PHAT Stereo is on. PCM Output Path and Mute. The POP bit controls the optional PCM out 3D bypass path (the pre- and post-3D PCM out paths are mutually exclusive). 0 = pre-3D 1 = post-3D.
MIX
3D
POP
3D Control Register (Index 22h)
Reg Name Num 22h 3D Control D15 X D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 DP3 D2 D2 DP2 D1 D1 DP1 D0 D0 DP0 Default 0000h
DP[2:0]
Depth Control. Sets 3D "Depth" PHAT Stereo enhancement according to table below. DP3 . . . DP0 0000 0001 . . 14 15 Depth 0% 6.67% . . 93.33% 100%
REV. 0
-17-
AD1885
Subsection Ready Register (Index 26h)
Reg Name Num 26h D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 X D5 D5 X D4 D4 X D3 D3 REF D2 D2 ANL D1 D1 D0 D0 Default
Power-Down Cntrl/Stat EAPD PR6
PR5 PR4 PR3 PR2 PR1 PR0 X
DAC ADC 000xh
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1885 subsections. If the bit is a one, then that subsection is "ready." Ready is defined as the subsection able to perform in its nominal state. ADC DAC ANL REF PR[5:0] ADC section ready to transmit data. DAC section ready to accept data. Analog gainuators, attenuators, and mixers ready. Voltage References, VREF and VREFOUT up to nominal level. AD1885 Power-Down Modes. The first three bits are to be used individually rather than in combination with each other. The last bit PR3 can be used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until the reference is up. PR0 - Power-Down ADC PR1 - Power-Down DAC PR2 - Power-Down Analog Mixer PR3 - Power-Down VREF and VREFOUT PR4 - Power-Down AC-Link PR5 - Power-Down Internal Clock PR6 - Power-Down Headphone EAPD - External AMP Power-Down Control Signal PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can either be up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set. In multiple-codec systems, the master codec's PR5 and PR4 bits control the slave codec. PR5 is also effective in the slave codec if the master's PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5. Power-Down State ADC Power-Down DAC Power-Down ADC and DAC Power-Down Mixer Power-Down ADC + Mixer Power-Down DAC + Mixer Power-Down ADC + DAC + Mixer Power-Down Standby
Extended Audio ID Register (Index 28h)
Reg Name Num 28h Extended Audio ID D15 ID1 D14 ID0 D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 VRA Default 0001h
EAPD PR6 X X X X X X X X 0 0 0 0 0 0 0 1
PR5 0 0 0 0 0 0 0 1
PR4 0 0 0 0 0 0 0 1
PR3 0 0 0 0 0 0 0 1
PR2 0 0 0 1 1 1 1 1
PR1 0 1 1 0 0 1 1 1
PR0 1 0 1 0 1 0 1 1
Note: The Extended Audio ID is a read only register. VRA ID[1:0] Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio. ID1, ID0 is a 2-bit field that indicates the codec configuration: Primary is 00; Secondary is 01.
-18-
REV. 0
AD1885
Extended Audio Status and Control Register (Index 2Ah)
Reg Name Num 2Ah Extended Audio St/Ctrl D15 X D14 X D13 X D12 X D11 X D10 X D9 D9 X D8 D8 X D7 D7 X D6 D6 X D5 D5 X D4 D4 X D3 D3 X D2 D2 X D1 D1 X D0 D0 VRA Default 0000h
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio features. VRA Variable Rate Audio. VRA = 1 enables support for Variable Rate Audio mode (sample rate control registers and SLOTREQ signaling).
PCM DAC Rate Register (Index 2Ch)
Reg Num Name D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
2Ch/(7Ah) PCM DAC Rate
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg Num 32h/(78h) Name PCM ADC Rate D15 SR15 D14 SR14 D13 SR13 D12 SR12 D11 SR11 D10 SR10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR[15:0] Writing to this register allows programming of the sampling frequency from 7040 Hz (1B80h) to 48 kHz (BB80h) in 1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (BB80h) causes the codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back when read; otherwise, the closest rate supported is returned.
Jack Sense/Audio Interrupt/Status Register (Index 72h)
Reg Num
Name
D15
D14 JS0_ OUT
D13
D12
D11
D10
D9 D9
D8 D8
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0 JS JS INT
Default
72h
Jack Sense/Audio JS1_OUT/ Interrupt/Status FUNCT
JS1 JS0 JS1_ JS0_ JS1 PUDIS PUDIS OE OE DIS OE OE
JS0 JS1 JS0 JS1 JS0 AUD DIS CLR CLR MODE MODE INT
JS1 JS0
0000h
Note: all register bits are read/write except for AUDINT, JSINT, JS0 and JS1, which are read only. JSINT JS0 JS1 AUDINT JS0MODE JS1MODE JS0CLR JS1CLR JS0DIS JS1DIS REV. 0 Indicates that a jack sense interrupt has been generated by JS0 or JS1. Remains set until all JS enabled interrupts are cleared. Indicates Pin JS0 state. Indicates Pin JS1 state. Indicates the Codec has generated audio interrupt. Remains set until software clears all pending interrupts. Sets JS0 pin input mode, 1 = Interrupt 0 = Jack Sense. Sets JS1 pin input mode, 1 = Interrupt 0 = Jack Sense. This bit is set by the Codec when there is a pending JS0 interrupt. Software must clear this bit to clear the JS0 interrupt status bit. This bit is set by the Codec when there is a pending JS1 interrupt. Software must clear this bit to clear the JS1 interrupt status bit. If the JS0DIS bit is set, the Codec ignores Jack Sense pin JS0. If the JS1DIS bit is set, the Codec ignores Jack Sense pin JS1. -19-
AD1885
JS0_OE JS1_OE JS0PUDIS JS1PUDIS JS0_OUT Enables JS0 pin as a general-purpose output. Enables JS1 pin as a general-purpose output. Setting the JS0PUDIS bit disables the JS0 pin internal pull-up. Setting the JS1PUDIS bit disables the JS1 pin internal pull-up. When enabled as GPO, the JS0 pin reflects the state of the JS0_OUT bit.
JS1_OUT/FUNCT When enabled as GPO, the JS1 pin reflects the state of the JS1_OUT bit, otherwise this bit can be set to change the functionality of JS1 so that only LINE_OUT is muted when JS1 is high.
Serial Configuration (Index 74h)
Reg Num 74h Name Serial Configuration D15 SLOT 16 16 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
REGM2
REGM1
REGM0
X
X
DHWR
X
X
X
X
X
X
X
X
X
X
Note: this register is not reset when the reset register (register 00h) is written. DHWR REGM0 REGM1 REGM2 SLOT16 Disable Hardware Reset. Master Codec register mask. Slave 1 Codec register mask. Slave 2 Codec register mask. Enable 16-bit slots.
If your system uses only a single AD1885, you can ignore the register mask. SLOT16 makes all AC-Link slots 16 bits in length, formatted into 16 slots.
Miscellaneous Control Bits (Index 76h)
Reg Name Num 76h Misc Control Bits D15 DAC Z D14 LPMI X D13 D12 X D11 D10 D9 D9 D8 D8 ALSR D7 D7 MOD EN EN D6 D6 D5 D5 D4 D4 X D3 D3 X D2 D2 DRSR D1 D1 X D0 D0 ARSR Default 0000h
DAM DMS DLSR X
SRX10 SRX8 D7 D7 D7 D7
ARSR
ADC right sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). DAC right sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). Multiply SR1 rate by 8/7. Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive. Modem filter enable (left channel only). Change only when DACs and ADCs are powered down. ADC left sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). DAC left sample generator select 0 = SR0 Selected (32h) 1 = SR1 Selected (2Ch). Digital Mono Select. 0 = Mixer 1 = Left DAC and Right DAC. Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output. Low Power Mixer. Zero fill (vs. repeat) if DAC is starved for data.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
DMS
DAM LPMIX DACZ
-20-
REV. 0
AD1885
Sample Rate 0 (Index 78h)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default
(32h)/78h Sample Rate 0 SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR0[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
Reg Num Name D15 D14 D13 D12 D11 D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D2 D2 D1 D1 D0 D0 Default
(2Ch)/7Ah Sample Rate 1 SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample rates are reset to 48 kHz. SR1[15:0] Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Vendor ID Registers (Index 7Ch-Eh)
Reg Name Num 7Ch Vendor ID1 D15 F7 F7 D14 F6 F6 D13 F5 F5 D12 F4 F4 D11 F3 F3 D10 F2 F2 D9 D9 F1 F1 D8 D8 F0 F0 D7 D7 S7 S7 D6 D6 S6 S6 D5 D5 S5 S5 D4 D4 S4 S4 D3 D3 S3 S3 D2 D2 S2 S2 D1 D1 S1 S1 D0 D0 S0 S0 Default 4144h
S[7:0] F[7:0]
Reg Name Num 7Eh
This register is ASCII encoded to "S." This register is ASCII encoded to "D."
D15 D14 T6 T6 D13 T5 T5 D12 T4 T4 D11 T3 T3 D10 T2 T2 D9 D9 T1 T1 D8 D8 T0 T0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Default
Vendor ID2 T7 T7
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5360h
T[7:0] REV[7:0]
This register is ASCII encoded to "S." Revision Register field contains the revision number.
These bits are read-only and should be verified before accessing vendor defined features.
REV. 0
-21-
AD1885
APPLICATIONS CIRCUITS
The AD1885 has been designed to require a minimum amount of external circuitry. The recommended applications circuits are shown in Figures 9-18. Reference designs for the AD1885 are available and may be obtained by contacting your local Analog Devices sales representative or authorized distributor. Example shell programs for establishing a communications path between the AD1885 and an ADSP-21xx or ADSP-21xxx are also available.
AVDD + NOTE: IF NOT USED, GROUND JACK SENSE PINS.
NC NC
+ 22pF 1 2 3 4 5 6 7 8 9 10 11 12
JS1 JSO/EAPD ID1 ID0 AVSS3 AVDD3 NC HP_OUT_R AVSS2 HO_OUT_L AVDD2 MONO_OUT
48 47 46 45 44 43 42 41 40 39 38 37
DVDD
NC
22pF
24.576MHz
47pF 10k PC_BEEP
PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R
SDATA_OUT SDATA_IN SYNC RESET BIT_CLK
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
AD1885
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
36 35 34 33 32 31 30 29 28 27 26 25
47nF +
270pF NPO 270pF NPO
+
+
AVDD
13 14 15 16 17 18 19 20 21 22 23 24
FB 600Z
NOTE: ALL "UNUSED" ANALOG INPUTS (LINE_IN_L/R, AUX_L/R, VIDEO_L/R, MIC1, MIC2, PC_BEEP, PHONE_IN AND CD_L/R/GND) MUST BE LEFT UNCONNECTED.
Figure 9. Recommended One-Codec PWR/Decoupling and AC`97 Connections
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AD1885
JACK SENSE OPERATION
The AD1885 features two Jack Sense pins (JS0 and JS1) that can be used to automatically mute the LINE_OUT and/or MONO_OUT audio outputs. When the Jack Sense pins are connected to the output jacks, the AD1885 can sense whether an audio plug has been inserted into a particular output jack and automatically mute the other unnecessary audio outputs. The JS1 pin should normally be connected to the HP_OUT jack to automatically mute the MONO_OUT and LINE_OUT audio signals, while the JS0 pin should normally be connected to the LINE_OUT jack to automatically mute the MONO_OUT signal. It is also possible to set the D15 bit in the Jack Sense Index Register (72h), which causes JS1 to only mute the LINE_OUT signal. This option may be desirable in certain audio configurations. Table I summarizes the Jack Sense operation.
Table I. Jack Sense Operation Table
HP_OUT Plug (JS1) OUT
LINE_OUT Plug (JS0) OUT
Audio Output States (REG 72h, D15 = 0) HP_OUT = ON LINE_OUT = ON MONO_OUT = ON HP_OUT = ON LINE_OUT = ON MONO_OUT = MUTE HP_OUT = ON LINE_OUT = MUTE MONO_OUT = MUTE HP_OUT = ON LINE_OUT = MUTE MONO_OUT = MUTE
Audio Output States (REG 72h, D15 = 1) HP_OUT = ON LINE_OUT = ON MONO_OUT = ON HP_OUT = ON LINE_OUT = ON MONO_OUT = MUTE HP_OUT = ON LINE_OUT = MUTE MONO_OUT = ON HP_OUT = ON LINE_OUT = MUTE MONO_OUT = MUTE
OUT
IN
IN
OUT
IN
IN
NOTE: PLUG IN = JACK SENSE HIGH, PLUG OUT = JACK SENSE LOW.
The Jack Sense inputs are active high and their functionality is enabled by default on CODEC power-up. If necessary, the Jack Sense inputs can be individually disabled by writing to the D8 and D9 bits on the CODEC Jack Sense Index Register (72h). The Jack Sense pins contain active internal pull-ups. If the Jack Sense inputs are not being used, they should be pulled down to digital ground using 10 k resistors. This prevents LINE_OUT and MONO_OUT from becoming muted while the Jack Senses are enabled.
CONNECTING THE JACK SENSES TO THE OUTPUT JACKS Headphone Jack
The diagram on Figure 10 shows the preferred method to connect the JS1 Jack Sense line to the HP_OUT jack. This scheme requires a stereo jack with a normally closed and isolated single switch. The switch holds the Jack Sense line low (grounded) until an audio plug is inserted, causing the switch to open and the Jack Sense line to go high due to the CODEC internal pull-up. The R2 and R3 resistors keep the electrolytic output caps properly polarized while the HP_OUT jack is not used.
NOTE: LOCATE R1 CLOSE TO CODEC. JACK SENSE LINE
TO CODEC JS1 (PIN 48)
OPTIONAL EMC COMPONENTS FROM CODEC HP_OUT_R (PIN 41) + L1 600Z FROM CODEC HP_OUT_L (PIN 39) 5 4 3 2 1
ISOLATED NC SWITCH
+ C1 470pF
L2 600Z C4 470pF
HEADPHONE OUT
Figure 10. Jack Sense Connection to HP_OUT Jack, Using Isolated Switch
Alternatively, when an audio output jack containing an isolated switch is not available, the circuit shown on Figure 11 can be used. While the audio plug is out, this circuit keeps the Jack Sense line state low, by the pull-down affect of R2 (with no audio present) or by tracking the lower peaks of the HP_OUT audio signal. Once an audio plug is inserted and the jack switch opens, the Jack Sense line switches to a high state due to the CODEC internal pull-up, which quickly charges C1 to DVDD. The R2 and R3 resistors also keep the electrolytic output caps properly polarized while the HP_OUT jack is not used. REV. 0 -23-
AD1885
NOTE: LOCATE R1 AND C1 CLOSE TO CODEC. JACK SENSE D1 TO CODEC JS1 (PIN 48) MMBD914 OPTIONAL EMC COMPONENTS L1 600Z FROM CODEC HP_OUT_R (PIN 41) + C4 470pF L2 600Z FROM CODEC HP_OUT_L (PIN 39) + C5 470pF 1 2 3 4 5 J1
HEADPHONE OUT
Figure 11. Jack Sense Connection to HP_OUT Jack, Using Nonisolated Switch
LINE_ OUT Jack
Although not shown, if a LINE_OUT jack is used and the jack sense functionality is desired, the LINE_OUT jack should be wired in a similar configuration as shown above for the HP_OUT jack (preferably Figure 10). The LINE_OUT jack should normally be connected to the JS0 input, in order to mute the MONO_OUT signal. We recommend that in this case the output coupling caps (C2, C3) be set to 2.2 F. All other values should be kept the same.
APPLICATION CIRCUITS
CD-ROM CONNECTIONS
Typical CD-ROM drives generate 2 V rms output and require a voltage divider for compatibility with the Codec input (1 V rms range). The recommended circuit is basically a group of divide-by-two voltage dividers as shown on Figure 12. The CD_GND_REF pin is used to cancel differential ground noise from the CD-ROM. For optimum noise cancellation, this section of the divider should have approximately half the impedance of the right and left channel section dividers.
VOLTAGE DIVIDER AC-COUPLING
TO CODEC CD_L INPUT
HEADER FOR CD ROM AUDIO (LGGR)
1 2 3 4
TO CODEC CD_GND_REF INPUT
TO CODEC CD_R INPUT
Figure 12. Typical CD-ROM Audio Connections
LINE_IN, AUX AND VIDEO INPUT CONNECTIONS
Most of these audio sources also generate 2 V rms audio level and require a -6 dB input voltage divider to be compatible with the Codec inputs. Figure 13 shows the recommended application circuit. For applications requiring EMC compliance, the EMC components should be configured and selected to provide adequate RF immunity and emissions control.
EMC COMPONENTS LINE/AUX/VIDEO INPUT J1 1 2 3 4 5 L2 600Z TO CODEC RIGHT CHANNEL INPUT C1 470pF L1 600Z TO CODEC LEFT CHANNEL INPUT C2 470pF VOLTAGE DIVIDER AC-COUPLING
Figure 13. LINE_IN, AUX, and Video Input Connections
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AD1885
MICROPHONE CONNECTIONS
The AD1885 contains an internal microphone preamp with 20 dB gain; in most cases a direct microphone connection as shown in Figure 14 is adequate. If the microphone level is too low, an external preamp can be added as shown in Figure 15. In either case the microphone bias can be derived from the Codec's internal reference (VREFOUT) using a 2.2 k resistor. For the preamp circuit, the VREFOUT signal can also provide the midpoint bias for the amplifier. To meet the PC99 1.0A requirements, the MIC signal should be placed on the microphone jack tip and the bias on the ring. This configuration supports electret microphones with three conductor plugs, as well as dynamic microphones with two conductor plugs (ring and sleeve shorted together). Additional filtering may be required to limit the microphone response to the audio band of interest.
EMC COMPONENTS J1 1 2 3 4 5 MIC INPUT L1 600Z C2 470pF L2 600Z C1 470pF MIC BIAS TO CODEC MIC1 OR MIC2 INPUT AC-COUPLING
FROM CODEC VREFOUT
Figure 14. Recommended Microphone Input Connections
PREAMP EMC COMPONENTS J1 1 2 3 4 5 MIC INPUT L1 600Z C2 470pF L2 600Z C1 470pF MIC BIAS U1 AD8531 AC-COUPLING
AVDD 4 TO CODEC MIC1 OR MIC2 INPUT
FROM CODEC VREFOUT
Figure 15. Microphone with Additional External Preamp (20 dB Gain)
LINE OUTPUT CONNECTIONS
The AD1885 Codec provides stereo LINE_OUT signals at a standard 1 V rms level. These signals must be ac-coupled before they can be connected to an external load. After the ac-coupling, a minimal resistive load is recommend to keep the capacitors properly biased and reduce click and pop when plugging stereo equipment into the output jack. The capacitor values should be selected to provide a desired frequency response, taking into account the nominal impedance of the external load. To meet the PC99 specification for PCs, testing must be performed with a 10 k load, therefore a 1 F value is recommended to achieve less than -3 dB roll-off at 20 Hz.
EMC COMPONENTS STEREO LINE_OUT JACK J1 L2 600Z C1 470pF L1 600Z C2 470pF FROM CODEC LINE_OUT_L NOTE: IF AN OUTPUT AMP IS USED, THE AC-COUPLING CAP VALUES WILL DEPENDEND ON THE AMP DESIGN. FROM CODEC LINE_OUT_R AC-COUPLING
Figure 16. Recommended LINE_OUT Connections
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AD1885
PC_BEEP INPUT CONNECTIONS
The recommended PC_BEEP input circuit is shown below. Under most cases the PC_BEEP signal should be attenuated, filtered and then ac-coupled into the Codec.
PC_BEEP (FROM ICH)
TO CODEC PC_BEEP INPUT
Figure 17. Recommended PC_BEEP Connections
GROUNDING AND LAYOUT
To reduce noise and emissions, Analog Devices recommends a split ground plane as shown in Figure 18. The purpose of splitting the ground plane is to create a low noise analog area that is somewhat isolated from the digital ground current noise generated by the system's logic. All the analog circuitry should be placed on the analog ground plane area. For reference purposes, and to return power supply currents, the analog and digital ground planes must be connected at some point, ideally a small bridge under or near the Codec should be provided. A 0 resistor or a ferrite bead should also be considered since these allow some flexibility in optimizing the layout to meet EMC requirements.
DIGITAL GROUND PLANE
CONNECT SPLIT GROUND PLANES AT OR NEAR CODEC.
PIN 1
ISOLATION TRENCH
AD1885
ANALOG GROUND PLANE
Figure 18. Recommended Split Ground Plane
ANALOG POWER SUPPLY
To minimize audio noise, the Codec analog power supply (AVDD) should be well decoupled and regulated. In PC systems it is recommended that the analog supply be derived from the 12 V PC power supply using a localized linear voltage regulator. Preferably, the analog power supply should be connected to the Codec's analog section using a ferrite bead. If a power plane layer is being used in the system design, it is recommended that the analog power plane for the Codec also be split (mirroring the analog ground plane). In this case, the analog power supply ferrite bead should bridge the isolation trench, close to the Codec location.
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AD1885
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) SEATING PLANE TOP VIEW
(PINS DOWN)
0.354 (9.00) BSC 0.276 (7.0) BSC
48 1 37 36
0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
0.006 (0.15) 0.002 (0.05) 0 -7
0 MIN 0.007 (0.18) 0.004 (0.09)
12 13
25 24
0.019685 (0.5) BSC
0.011 (0.27) 0.006 (0.17)
0.354 (9.00) BSC
0.276 (7.0) BSC
REV. 0
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PRINTED IN U.S.A.
C00753-2.5-7/00 (rev. 0)

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